HY64UD16322M Datasheet - Hynix Semiconductor

HY64UD16322M - 2M x 16 bit Low Low Power 1T/1C Pseudo SRAM

- Power Up & Deep Power Down Exit Sequence Mar.

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‘ 02 Final Feb.

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‘ 02 Preliminary Dec.

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‘ 01 Preliminary Nov.

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’ 01 Preliminary Oct.

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’ 01 Preliminary Jul.

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’ 01 Preliminary Draft Date Jan.

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’ 01 Remark Preliminary Preliminary This document is a general product

www.DataSheet4U.com HY64UD16322M Series Document Title 2M x 16 bit Low Low Power 1T/1C Pseudo SRAM Revision history Revision No.

History 1.0 1.1 Initial Revised - Change Pin Connection - Improve tOE from 45ns to 30ns - Correct State Diagram 1.2 Revised - Correct Package Dimension - Change Absolute Maximum Ratings 1.3 Revised - DC Electrical Characteristics (ISB1,IDPD,ICC1) - State Diagram - Power Up Sequence - Deep Power Down Sequence - Read/Write Cycle Note - Release standby current from 100

HY64UD16322M Features

* CMOS Process Technology

* 2M x 16 bit Organization

* TTL compatible and Tri-state outputs

* Deep Power Down : Memory cell data hold invalid

* Standard pin configuration : 48-FBGA

* Data mask function by /LB, /UB PRODUCT FAMILY Product No. HY64UD1632

HY64UD16322M_HynixSemiconductor.pdf