HY64LD16162M Datasheet - Hynix Semiconductor

HY64LD16162M - 1M x 16 bit Low Low Power 1T/1C Pseudo SRAM

- Power Up & Deep Power Down Exit Sequence Mar.

11.

‘ 02 Final Feb.

27.

‘ 02 Preliminary Dec.

20.

‘ 01 Preliminary Nov.

14.

’ 01 Preliminary Oct.

07.

‘ 01 Preliminary Jul.18.

’ 01 Preliminary Draft Date Jan.

04.

’ 01 Jul.

03.

’ 01 Remark Preliminary Preliminary This document is a general product

www.DataSheet4U.com HY64LD16162M Series Document Title 1M x 16 bit Low Low Power 1T/1C Pseudo SRAM Revision history Revision No.

History 1.0 1.1 Initial Revised - Change Pin Connection - Improve tOE from 45ns to 30ns - Correct State Diagram 1.2 Revised - Correct Package Dimension - Change Absolute Maximum Ratings 1.3 Revised - DC Electrical Characteristics ( IDPD,ICC1) - State Diagram - Power Up Sequence - Deep Power Down Sequence - Read/Write Cycle Note 1.4 1.5 Revised - DC Electrical Charac

HY64LD16162M Features

* CMOS Process Technology

* 1M x 16 bit Organization

* TTL compatible and Tri-state outputs

* Deep Power Down : Memory cell data hold invalid

* Standard pin configuration : 48-FBGA

* Data mask function by /LB, /UB PRODUCT FAMILY Product No. HY64LD1616

HY64LD16162M_HynixSemiconductor.pdf