HY5MS7B2BLFP Datasheet (Hynix)

HY5MS7B2BLFP, Mobile DDR SDRAM

and figures Updated Status Register Rearranged pages to be more systematic Corrected editorial errors in descriptions and figures Corrected AC Input High/Low Level Voltage (VIH / VIL = 0.8 *VDDQ / 0.2 *VDDQ) - Updated IDD6 current - Updated tWTR in LPDDR333 - Reorganized and updated AC and DC

HY5MS7B2BLFP Features

* SUMMARY

* Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle

* Mobile DDR SDRAM INTERFACE - x32 bus width: HY5MS7B2BLFP www.DataSheet4U.com

* MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (