* SUMMARY
* Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle
* Mobile DDR SDRAM INTERFACE - x32 bus width: HY5MS7B2BLFP www.DataSheet4U.com
* MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (
HY5MS7B2BLFP Datasheet (1.56 MB)
HY5MS7B2BLFP
Hynix
1.56 MB
Mobile ddr sdram.
512Mbit MOBILE DDR SDRAM based on 4M x 4Bank x32 I/O
Document Title 512MBit (4Bank x 4M x 32bits) MOBILE DDR SDRAM Revision History
www.DataSheet4U.c.
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