HY5MS7B2BLF Datasheet - Hynix

HY5MS7B2BLF Mobile DDR SDRAM 512M

and figures Updated Status Register Rearranged pages to be more systematic Corrected editorial errors in descriptions and figures Corrected AC Input High/Low Level Voltage (VIH / VIL = 0.8 *VDDQ / 0.2 *VDDQ) - Updated IDD6 current - Updated tWTR in LPDDR333 - Reorganized and updated AC and DC.

HY5MS7B2BLF Features

* SUMMARY

* Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle

* Mobile DDR SDRAM INTERFACE - x32 bus width: HY5MS7B2BLFP www.DataSheet4U.com

* MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (

HY5MS7B2BLF Datasheet (1.56 MB)

HY5MS7B2BLF Datasheet Preview — Preview of HY5MS7B2BLF PDF

Datasheet Details

Part number:

HY5MS7B2BLF

Manufacturer:

Hynix

File Size:

1.56 MB

Description:

Mobile ddr sdram 512m.

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HY5MS7B2BLF Mobile DDR SDRAM 512M Hynix

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