Description
512Mbit MOBILE DDR SDRAM based on 4M x 4Bank x32 I/O Document Title 512MBit (4Bank x 4M x 32bits) MOBILE DDR SDRAM Revision History www.DataSheet4U.c.
and figures Updated Status Register Rearranged pages to be more systematic Corrected editorial errors in descriptions and figures Corrected AC Input.
Features
* SUMMARY
* Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle
* Mobile DDR SDRAM INTERFACE - x32 bus width: HY5MS7B2BLFP
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* MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (
Applications
* which use the battery such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, hand-held PCs. It is organized as 4banks of 4,194,304 x32. The HYNIX HY5MS7B2BLF(P) series uses a double-data-rate architecture to achieve high-speed operation. The double
