* DESCRIPTION:
* Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
* Distributes one clock input to one bank of ten outputs
* Output enable bank control
* External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal
IDTCSP2510D Datasheet (91.80 KB)
IDTCSP2510D
IDT
91.80 KB
3.3v phase-lock loop clock driver.
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IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER
0°C TO 85°C TEMPERATURE RANGE
3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER.
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