* DESCRIPTION: The CSPT855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes one differential clock input pair(CLK, CLK ) to four differential output pairs (Y [0:3], Y [0:3]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). When PWRDWN is high, the ou
IDTCSPT855 Datasheet (105.40 KB)
IDTCSPT855
Integrated Device Technology
105.40 KB
2.5v phase locked loop clock driver.
IDTCSPT855 2.5V PLL CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
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2.5V PHASE LOCKED LOOP CLOCK DRIVER
IDTCSPT855
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