IDTCSPF2510C Datasheet (Integrated Device Technology) - 3.3V PHASE-LOCK LOOP CLOCK DRIVER

IDTCSPF2510C, 3.3V PHASE-LOCK LOOP CLOCK DRIVER

The IDTCSPF2510C is a high performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.

It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

The CSPF2510C o

IDTCSPF2510C Features

* Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications

* Distributes one clock input to one bank of ten outputs

* Output enable bank control

* External feedback (FBIN) pin is used to synchronize the output to the clock input signal

* On-chip