* Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
* Distributes one clock input to one bank of ten outputs
* Output enable bank control
* External feedback (FBIN) pin is used to synchronize the output to the clock input signal
* On-chip
IDTCSPF2510C Datasheet (100.89 KB)
IDTCSPF2510C
Integrated Device Technology
100.89 KB
3.3v phase-lock loop clock driver.
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IDTCSPF2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER
0ºC TO 85ºC TEMPERATURE RANGE
3.3V PHASE-LOCK LOOP CLOCK DRIVER
IDTCSPF2510C
F.
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