IS61QDB41M18A - 18Mb QUAD (Burst 4) SYNCHRONOUS SRAM
OCTOBER 2014 * 512Kx36 and 1Mx18 configuration available.
* On-chip Delay-Locked loop (DLL) for wide data valid window.
* Separate independent read and write ports with concurrent read and write operations.
* Synchronous pipeline read with late write operation.
* Double Data Ra
