IS61QDB41M36A - 36Mb QUAD SYNCHRONOUS SRAM
APRIL 2016 * 1Mx36 and 2Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data valid window.
* Separate independent read and write ports with concurrent read and write operations.
* Synchronous pipeline read with late write operation.
* Double Data Rate (
