Datasheet Details
| Part number | IS61QDB44M18C |
|---|---|
| Manufacturer | ISSI |
| File Size | 778.95 KB |
| Description | 72Mb QUAD SYNCHRONOUS SRAM |
| Datasheet |
 IS61QDB44M18C-ISSI.pdf
|
| Part number | IS61QDB44M18C |
|---|---|
| Manufacturer | ISSI |
| File Size | 778.95 KB |
| Description | 72Mb QUAD SYNCHRONOUS SRAM |
| Datasheet |
IS61QDB44M18C-ISSI.pdf
|
APRIL 2018 2Mx36 and 4Mx18 configuration available. Separate independent read and write ports with concurrent read and write operations. Max. Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and write input ports. 1.5 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control regist
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