IS61QDPB24M18A - 72Mb QUADP (Burst 2) Synchronous SRAM

ISSI

IS61QDPB24M18A Datasheet Preview — Preview of IS61QDPB24M18A PDF

Datasheet Details

Part number	IS61QDPB24M18A
Manufacturer	ISSI
File Size	607.77 KB
Description	72Mb QUADP (Burst 2) Synchronous SRAM
Datasheet	IS61QDPB24M18A-ISSI.pdf

IS61QDPB24M18A Product details

Description

at page 6 for each ODT option.DESCRIPTION The and are synchronous, high- performance CMOS static random access memory (SRAM) devices.These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.Refer to the for a description of the basic operations of these SRAMs.Read and write addresses are registered on alternating rising edges of the K clock.Read a

Features

2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
2.5 Cycle read latency.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and cont.

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Published: Jun 10, 2016 |