IS61QDPB24M18A1 Datasheet - ISSI

IS61QDPB24M18A1 72Mb QUADP (Burst 2) Synchronous SRAM

at page 6 for each ODT option. DESCRIPTION The and are synchronous, high- performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all int.

IS61QDPB24M18A1 Features

* 2Mx36 and 4Mx18 configuration available.

* On-chip Delay-Locked Loop (DLL) for wide data valid window.

* Separate independent read and write ports with concurrent read and write operations.

* Synchronous pipeline read with EARLY write operation.

* Double Data Rate (DDR) interfa

IS61QDPB24M18A1 Datasheet (607.77 KB)