IS61QDPB24M18C - 72Mb QUADP Synchronous SRAM

ISSI

Datasheet Details

at page 6 for each ODT option.

2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Max. 450 MHz clock for high bandwidth.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
2.5 Cycle read latency.
Fixed 2-bit burst for read and write operations.
Two input clocks (K and K#) fo.

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Published: Feb 18, 2024 |