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NDL28P - 2Gb (x8) DDR3L Synchronous DRAM

Datasheet Summary

Features

  • including full backward compatibility to DDR3. Hereafter the device will be referred to as DDR3L for both part numbers. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pair in a source synchronous fashion. These devices operate with a single +1.35V -0.067V / +0.1V power supply and are available in.

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Datasheet Details

Part number NDL28P
Manufacturer Insignis
File Size 2.25 MB
Description 2Gb (x8) DDR3L Synchronous DRAM
Datasheet download datasheet NDL28P Datasheet
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Full PDF Text Transcription

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2Gb (x8) - DDR3/DDR3L Synchronous DRAM 256M x 8 bit DDR3/3L Synchronous DRAM Overview The 2Gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM. The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications. The chip is designed to comply with all DDR3L DRAM key features, including full backward compatibility to DDR3. Hereafter the device will be referred to as DDR3L for both part numbers. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
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