ICS9FG108 - Programmable FTG for Differential P4 CPU
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN NAME XIN/CLKIN X2 VDD GND REFOUT FS2 OE_7 * * DIF_7 DIF_7# VDD DIF_6 DIF_6# OE_6 * VDD GND OE_5 * DIF_5 DIF_5# VDD DIF_4 DIF_4# OE_4 * * SDATA SCLK PIN TYPE IN OUT PWR PWR OUT IN IN OUT OUT PWR OUT OUT IN PWR
www.DataSheet4U.com Integrated Circuit Systems, Inc.
ICS9FG108 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks Recommended Application: Pin Configuration XIN/CLKIN X2 VDD GND REFOUT FS2 OE_7 DIF_7 DIF_7# VDD DIF_6 DIF_6# OE_6 VDD GND OE_5 DIF_5 DIF_5# VDD DIF_4 DIF_4# OE_4 SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDA GNDA IREF FS0 FS1 O
ICS9FG108 Features
* Generates common frequencies from 14.318 MHz or 25 MHz
* Crystal or reference input
* 8 - 0.7V current-mode differential output pairs
* Supports Serial-ATA at 100 MHz
* Two spread spectrum modes: 0 to -0.5 downspread and +/-0.25% centerspread
* Unus
