IDTCV104B Datasheet - Integrated Device Technology

IDTCV104B CLOCK GENERATOR FOR DESKTOP PC PLATFORMS

KEY SPECIFICATION: * * * * CPU/SRC CLK cycle to cycle jitter < 125ps SATA CLK cycle to cycle jitter < 125ps PCI CLK cycle to cycle jitter < 250ps Static PLL frequency divide error as low as 36ppm FUNCTIONAL BLOCK DIAGRAM DataSheet4U.com PLL1 SSC EasyN Programming .

IDTCV104B Features

* 4 PLL architecture Linear frequency programming Independent frequency programming and SSC control Band-gap circuit for differential output High power-noise rejection ratio 66MHz to 533MHz

IDTCV104B_IntegratedDeviceTechnology.pdf

IDTCV104B Datasheet Preview — Preview of IDTCV104B PDF

Datasheet Details

Part number:

IDTCV104B

Manufacturer:

Integrated Device Technology

File Size:

213.18 KB

Description:

Clock generator for desktop pc platforms.

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TAGS

IDTCV104B IDTCV104B CLOCK GENERATOR FOR DESKTOP PLATFORMS Integrated Device Technology

IDTCV104B Distributor