IDTCV107E - CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
KEY SPECIFICATION: * * * * CPU/SRC CLK cycle to cycle jitter < 125ps SATA CLK cycle to cycle jitter < 125ps PCI CLK cycle to cycle jitter < 250ps Static PLL frequency divide error as low as 36 ppm FUNCTIONAL BLOCK DIAGRAM DataSheet4U.com PLL1 SSC EasyN Programming
IDTCV107E Features
* 4 PLL architecture Linear frequency programming Independent frequency programming and SSC control Band-gap circuit for differential output High power-noise rejection ratio 66MHz to 533MHz
