* 4 PLL architecture Linear frequency programming Independent frequency programming and SSC control Band-gap circuit for differential output High power-noise rejection ratio 66MHz to 533MHz
IDTCV107E Datasheet (215.39 KB)
IDTCV107E
Integrated Device Technology
215.39 KB
Clock generator for desktop pc platforms.
www.DataSheet4U.com IDTCV107E CLOCK GENERATOR FOR DESKTOP PC PLATFORMS COMMERCIAL TEMPERATURE RANGE CLOCK GENERATOR FOR DESKTOP PC PLATFORMS IDTCV.
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