IDTCV107E Datasheet - Integrated Device Technology

IDTCV107E CLOCK GENERATOR FOR DESKTOP PC PLATFORMS

KEY SPECIFICATION: * * * * CPU/SRC CLK cycle to cycle jitter < 125ps SATA CLK cycle to cycle jitter < 125ps PCI CLK cycle to cycle jitter < 250ps Static PLL frequency divide error as low as 36 ppm FUNCTIONAL BLOCK DIAGRAM DataSheet4U.com PLL1 SSC EasyN Programming.

IDTCV107E Features

* 4 PLL architecture Linear frequency programming Independent frequency programming and SSC control Band-gap circuit for differential output High power-noise rejection ratio 66MHz to 533MHz

IDTCV107E_IntegratedDeviceTechnology.pdf

IDTCV107E Datasheet Preview — Preview of IDTCV107E PDF

Datasheet Details

Part number:

IDTCV107E

Manufacturer:

Integrated Device Technology

File Size:

215.39 KB

Description:

Clock generator for desktop pc platforms.

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TAGS

IDTCV107E IDTCV107E CLOCK GENERATOR FOR DESKTOP PLATFORMS Integrated Device Technology

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