CD4096BMS Datasheet - Intersil Corporation

CD4096BMS - CMOS Gated J-K Master-Slave Flip-Flops

of ‘B’ Series CMOS Devices” CD4095BMS TOP VIEW 14 VDD 13 SET 12 CLOCK 11 K1 10 K2 9 K3 8 Q CD4096BMS TOP VIEW NC 1 RESET 2 J1 3 J2 4 J3 5 Q 6 VSS 7 14 VDD 13 SET 12 CLOCK 11 K1 10 K2 9 K3 8 Q NC = NO CONNECTION Applications * Registers * Counters * Control Circuits SET 3 .

CD4096BMS Features

* Set-Reset Capability

* High Voltage Types (20V Rating)

* CD4095BMS Non-Inverting J and K Inputs

* CD4096BMS Inverting and Non-Inverting J and K Inputs

* 16MHz Toggle Rate (Typ.) at VDD - VSS = 10V

* Gated Inputs

* 100% Tested for Quiescent Cu

CD4096BMS_IntersilCorporation.pdf