ISL90840 Datasheet - Intersil

ISL90840 XDCP

TSSOP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SYMBOL RH3 RL3 RW3 A2 SCL SDA GND RW2 RL2 RH2 RW1 RL1 RH1 A0 A1 VCC D.N.C. RH0 RL0 RW0 ISL90840 DESCRIPTION “High” terminal of DCP3 “Low” terminal of DCP3 “Wiper” terminal of DCP3 Device address for the I2C interface I2C interface clock.

POSSIOBBLSEOSLUEBXTS9E5TP8IT4RU0OTDEUPDCRaTOtaDSUhCeTet ISL90840 Quad Digitally Controlled Potentiometers (XDCP™) November 14, 2006 FN8086.2 Low Noise, Low Power I2C® Bus, 256 Taps The ISL90840 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. Ea.

ISL90840 Features

* Four potentiometers in one package

* 256 resistor taps - 0.4% resolution

* I2C serial interface - Three address pins, up to eight devices/bus - Write/Read capability

* Power-on preset to mid-scale (128 tap position)

* Wiper resistance: 70 typical @ 3.3V

ISL90840-Intersil.pdf