SY89874U Datasheet (Microchip) - Programmable Clock Divider/Fanout Buffer

SY89874U, Programmable Clock Divider/Fanout Buffer

This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622 MHz or higher) CML, LVPECL, LVDS, or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock.

Available divider rat

SY89874U Features

* Integrated Programmable Clock Divider and 1:2 Fanout Buffer

* Guaranteed AC Performance over Temperature and Voltage: - >2.5 GHz fMAX -