SY89875U Datasheet (Micrel Semiconductor) - IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER

SY89875U, IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER

This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider to create a lower speed version of the input clock.

Available divider ratios are 2, 4, 8 and 16, or

SY89875U Features

* Integrated programmable clock divider and 1:2 fanout buffer

* Guaranteed AC performance over temperature and voltage:

* > 2.0GHz fMAX

* < 200ps tr/tf

* < 15ps within device skew

* Low jitter design:

* < 10psPP total jitter

* < 1psRMS