SY89875U - IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER

Product Overview

Micrel Semiconductor

Datasheet Details

Part number	SY89875U
Manufacturer	Micrel Semiconductor
File Size	218.16 KB
Description	IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER
Datasheet	SY89875U Datasheet
Additional preview pages of the SY89875U datasheet.

Product details

Description

This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider to create a lower speed version of the input clock.

Features

Integrated programmable clock divider and 1:2 fanout buffer.
Guaranteed AC performance over temperature and voltage:.
> 2.0GHz fMAX.
< 200ps tr/tf.
< 15ps within device skew.
Low jitter design:.
< 10psPP total jitter.
< 1psRMS cycle-to-cycle jitter.
Unique input termination and VT Pin for DC-coupled and AC-coupled Inputs; CML, PECL, LVDS and HSTL.
LVDS compatible outputs.
TTL/CMOS inputs for selec.

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Published: Jan 31, 2007 |