SY89874U Datasheet (Micrel Semiconductor) - Programmable Clock Divider/Fanout Buffer

SY89874U, Programmable Clock Divider/Fanout Buffer

This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock.

Available divider ratio

SY89874U Features

* Integrated programmable clock divider and 1:2 fanout buffer

* Guaranteed AC performance over temperature and voltage:

* >2.5GHz fMAX