M2S56D20ATP75A Datasheet, Dram, Mitsubishi

M2S56D20ATP75A Features

• Dram - Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs

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M2S56D20ATP75A

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Mitsubishi

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824.59kb

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📄 Datasheet

Description:

256m double data rate synchronous dram. M2S56D20AKT is a 4-bank x 16,777,216-word x 4-bit, M2S56D30AKT is a 4-bank x 8,388,608-word x 8-bit, M2S56D40AKT is a 4-bank x 4,194,

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M2S56D20ATP75A

Mitsubishi

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M2S56D20AKT - 256M Double Data Rate Synchronous DRAM (Mitsubishi)
DDR SDRAM (Rev.1.0) Jul. '01 Preliminary M2S56D20/ 30/ 40AKT MITSUBISHI LSIs 256M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents a.

M2S56D20AKT-10 - 256M Double Data Rate Synchronous DRAM (Mitsubishi)
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