M2S56D20ATP75A, M2S 256M Double Data Rate Synchronous DRAM

Mitsubishi

Description

DDR SDRAM (Rev.1.0) Jul.'01 Preliminary M2S56D20/ 30/ 40AKT MITSUBISHI LSIs 256M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents a.
M2S56D20AKT is a 4-bank x 16,777,216-word x 4-bit, M2S56D30AKT is a 4-bank x 8,388,608-word x 8-bit, M2S56D40AKT is a 4-bank x 4,194,304-word x 16-bit.

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M2S56D20ATP75A Datasheet Preview — This datasheet PDF includes multiple part numbers: M2S56D20ATP75A, M2S. Please refer to the document for exact specifications by model.

Datasheet Specifications

Part number: M2S56D20ATP75A, M2S
Manufacturer: Mitsubishi
File Size: 824.59 KB
Datasheet: M2S-56D3.pdf
Description: 256M Double Data Rate Synchronous DRAM
Note: This datasheet PDF includes multiple part numbers: M2S56D20ATP75A, M2S.
Please refer to the document for exact specifications by model.

Features

* - Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each po

M2S56D20ATP75A Distributors

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M2S 256M Double Data Rate Synchronous DRAM Mitsubishi

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