M2S56D30TP-10 Datasheet - Mitsubishi

M2S56D30TP-10, 256M Double Data Rate Synchronous DRAM

DDR SDRAM (Rev.0.0) Sep.'99 Preliminary MITSUBISHI LSIs M2S56D20/ 30 TP 256M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are sub.
M2S56D20TP is a 4-bank x 16777216-word x 4-bit, M2S56D30TP is a 4-bank x 8388608-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interfac.

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Datasheet Details

Part number:

M2S56D30TP-10

Manufacturer:

Mitsubishi

File Size:

259.90 KB

Description:

256M Double Data Rate Synchronous DRAM

Features

* - Vdd=Vddq=2.5v±0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each po

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M2S56D30TP-10 256M Double Data Rate Synchronous DRAM Mitsubishi

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