MC100E156 Datasheet - Motorola

MC100E156 3-BIT 4:1 MUX-LATCH

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3ĆBit 4:1 MuxĆLatch The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. 950ps Max. D to Output .

MC100E156 Datasheet (106.51 KB)