MC100E151 - 6-BIT D REGISTER
The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs.
Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 (or both) go HIGH.
The asynchronous Master Reset (MR) makes all Q outputs go LOW.
The 100
MC100E151 Features
* 1100 MHz Min. Toggle Frequency
* Differential Outputs
* Asynchronous Master Reset
* Dual Clocks
* PECL Mode Operating Range:
* VCC = 4.2 V to 5.7 V with VEE = 0 V
* NECL Mode Operating Range:
* VCC = 0 V with VEE =
* 4.2 V to
