MPC2105A Datasheet - Motorola

MPC2105A 512KB and 1MB BurstRAM

Pin Locations 66, 67, 68, 69, 71, 72, 73, 74, 76, 77, 78, 80, 81, 82, 83, 155, 156, 157, 158, 160, 161, 162, 163, 165, 166, 167, 169, 170, 171 62 151 64, 65 149 172 59, 60 30, 56, 115, 144, 146 153, 154 98, 104, 110, 118, 126, 132, 138, 148 4, 5, 6, 7, 10, 11, 12, 14, 16, 17, 19, 20, 22, 24, 25, 26.

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MPC2105A/D 512KB and 1MB BurstRAM™ Secondary Cache Modules for PowerPC™ PReP/CHRP Platforms The MPC2105A/B and the MPC2106A/B are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. The MPC2105A/B and MPC2106A/B utilize synchronous BurstRAMs. The modules ar.

MPC2105A Features

* ead Cycle, Continue Burst Write Cycle, Suspend Burst Read Cycle, Suspend Burst NOTES: 1. X means Don’t Care. 2. All inputs except CG must meet set

* up and hold times for the low

* to

* high transition of clock (CLK0

* CLK4). 3. Wait states are inserted by suspending burst

MPC2105A_Motorola.pdf