MPC2105C Datasheet - Motorola

MPC2105C 512KB and 1MB BurstRAM

Pin Locations 66, 67, 68, 69, 71, 72, 73, 74, 76, 77, 78, 80, 81, 82, 83, 155, 156, 157, 158, 160, 161, 162, 163, 165, 166, 167, 169, 170, 171 62 151 64, 65 149 172 59, 60 30, 56, 115, 144, 146 153, 154 98, 104, 110, 118, 126, 132, 138, 148 4, 5, 6, 7, 10, 11, 12, 14, 16, 17, 19, 20, 22, 24, 25, 26.

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MPC2105C/D 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC™ PReP/CHRP Platforms The MPC2105C and the MPC2106C are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. The MPC2105C and MPC2106C utilize synchronous BurstRAMs. The modules are configu.

MPC2105C Features

* n’t care. 2. For a write operation following a read operation, CG must be high before the input data required set

* up time and held high through the input data hold time. ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V) Rating Power Supply Voltage Voltage Relative to VSS Output Cu

MPC2105C Datasheet (229.08 KB)