* SNR, 72 dBFS; SFDR, 86 dBc Sample rate up to 125 Msps 14-bit pipelined ADC core Clock input divider by 2 for less jitter contribution
* Single 3 V supply
* Flexible input voltage range: 1 V to 2 V (peak-to-peak).
* CMOS or LVDS DDR digi
ADC1410S Datasheet (329.72 KB)
ADC1410S
NXP ↗ Semiconductors
329.72 KB
Single 14-bit adc.
ADC1410S series
Rev. 03
* 12 April 2010
www.DataSheet4U.com
Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digi.
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