Description
ADC1412D065/080/105/125 Dual 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs Rev.02 * 4 June 2009 www.DataSheet4U.com O.
Features
* I I I I I I SNR, 73 dB SFDR, 90 dBc Sample rate up to 125 Msps Dual-channel14-bit pipelined ADC core Single 3 V supply Flexible input voltage range: 1 V to 2 V (p-p) with 6 dB programmable fine gain I CMOS or LVDS DDR digital outputs I INL ±1 LSB, DNL ±0.5 LSB (typical) I I I I I I Input bandwidth, 6Applications
* 1.5 005aaa040 1.5 005aaa041 0 dB 005aaa042 1 1 -40 0.5 0.5 0 0 -80 -0.5 -0.5 -1 -1 -120 -1.5 0 4000 8000 12000 16000 -1.5 0 4000 8000 12000 16000 0 10 20 30 f (MHz) 40 Fig 1. Integral Non-Linearity (INL) Fig 2. Differential Non-Linearity (DNL) Fig 3. Output spectrum:ADC1412D105 Distributors
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