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74AHCT573 Octal D-type transparent latch

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Description

INTEGRATED CIRCUITS DATA SHEET 74AHC573; 74AHCT573 Octal D-type transparent latch; 3-state Product specification File under Integrated Circuits, IC06.
74AHC573; 74AHCT573 The 74AHC/AHCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).

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Features

* ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V
* Balanced propagation delays
* All inputs have Schmitt-trigger actions
* Common 3-state output enable input
* Functionally identical t

Applications

* A Latch Enable (LE) input and an Output Enable (OE) input are common to all latches. The ‘573’ consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i. e. a latch output will c

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