NT5DS32M16CG - 512Mb DDR SDRAM

Nanya Techology

Datasheet Details

Die C of 512Mb.

DDR 512M bit, Die C, based on 90nm design rules.
Double data rate architecture: two data transfers per clock cycle.
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
DQS is edge-aligned with data for reads and is centeraligned with data for writes.
Differential clock inputs (CK and CK).
Four internal banks for concurrent operation.
Data mask (DM) for write data.

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