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ADC12DS065 - A/D Converter

Description

NOTE: This is Advance Information for products currently in development.

ALL specifications are design targets and are subject to change.

Features

  • 1 GHz Full Power Bandwidth Internal sample-and-hold circuit and precision reference Low power consumption Clock Duty Cycle Stabilizer Single +3.3V supply operation Offset binary or 2's complement output data format Serial LVDS Outputs 60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch) Key Specifications.
  • For ADC12DS105 Resolution Conversion Rate SNR (fIN = 240 MHz) SFDR (fIN = 240 MHz) Full Power Bandwidth Po.

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www.DataSheet4U.com ADC12DS065/ADC12DS080/ADC12DS095/ADC12DS105 Dual 12-Bit A/D Converter ADVANCE INFORMATION February 2007 ADC12DS065/ADC12DS080/ADC12DS095/ADC12DS105 Dual 12-Bit, 65/80/95/105 MSPS A/D Converter with Serial LVDS outputs General Description NOTE: This is Advance Information for products currently in development. ALL specifications are design targets and are subject to change. The ADC12DS065, ADC12DS080, ADC12DS095, and ADC12DS105 are high-performance CMOS analog-to-digital converters capable of converting two analog input signals into 12-bit digital words at rates up to 65/80/95/105 Mega Samples Per Second (MSPS) respectively. The digital outputs are serialized and provided on differential LVDS signal pairs.
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