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CGS701V Low Skew PLL 1 to 8 CMOS Clock Driver

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Description

,..o ~ o ~DNaStemiicoonnduactlor PRELIMINARY CGS701V Commercial/CGS701TV Industrial Low Skew PLL 1 to 8 CMOS Clock Driver General .
CGS701 is an off the shelf clock driver specifically designed for today's high speed designs.

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Datasheet Specifications

Part number
CGS701V
Manufacturer
National Semiconductor
File Size
178.40 KB
Datasheet
CGS701V-NationalSemiconductor.pdf
Description
Low Skew PLL 1 to 8 CMOS Clock Driver

Features

* Guaranteed and tested: 500 ps pin-to-pin skew (tOSHL and tOSLH) on 1X out- puts. ± 500 ps propagation delay
* Output buffer of eight drivers for large fanout
* 25 MHz-160 MHz output frequency range
* Outputs operating at 4X, 2X, 1X of the reference frequency for mul

Applications

* Selectable output frequency
* Internal loop filter to reduce noise and jitter
* Separate analog and digital Vee and ground pins
* Low frequency test mode by disabling the PLL
* Implemented on National's Core CMOS process
* Symmetric output current dr

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