CGS701V - Low Skew PLL 1 to 8 CMOS Clock Driver
CGS701 is an off the shelf clock driver specifically designed for today's high speed designs.
It provides low skew outputs which are produced at different frequencies from three fixed input references.
The XTALIN input pin is designed to be driven from a 15 MHz-50 MHz crystal oscillator.
The PLL,
CGS701V Features
* Guaranteed and tested: 500 ps pin-to-pin skew (tOSHL and tOSLH) on 1X out- puts. ± 500 ps propagation delay
* Output buffer of eight drivers for large fanout
* 25 MHz-160 MHz output frequency range
* Outputs operating at 4X, 2X, 1X of the reference frequency for mul
