DS90LV001 - 3.3V LVDS-LVDS Buffer

National Semiconductor

Datasheet Details

The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal.

n n n n n n n Single +3.3 V Supply LVDS receiver inputs accept LVPECL signals TRI-STATE outputs Receiver input threshold < ± 100 mV Fast propagation delay of 1.4 ns (typ) Low jitter 800 Mbps fully differential data path 100 ps (typ) of pk-pk jitter with PRBS = 223.
1 data pattern at 800 Mbps n Compatible with ANSI/TIA/EIA-644-A LVDS standard n 8 pin SOIC and space saving (70%) LLP package n Industrial Temperature Range Connection Diagram Top View DS101338-5 Order Number DS90LV001TM, DS.

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