* 2000 1000 Coss 0
* 10
* 5 Crss 0 5 10 15 20 25 VGS VDS GATE
* TO
* SOURCE OR DRAIN
* TO
* SOURCE VOLTAGE (VOLTS) Figure 7a. Low Voltage Capacitance Variation 10000 1000 VGS = 0 V TJ = 25°C Ciss Coss 100 Crss 10 0 10 100 10 VDS, DRAIN
* TO
MTV16N50E Datasheet (261.31 KB)
MTV16N50E
261.31 KB
Power field effect transistor.
MTV16N50E
Advance Information TMOS E
*FET.™ Power Field Effect Transistor D3PAK for Surface Mount
N
*Channel Enhancement
*Mode Si.
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