NB2304A - Zero Delay Clock Buffer
Pin # 1 2 3 4 5 Pin Name REF (Note 1) CLKA1 (Note 2) CLKA2 (Note 2) GND CLKB1 (Note 2) CLKB2 (Note 2) VDD FBK Description Input reference frequency, 5 V tolerant input.
Buffered clock output, Bank A.
Buffered clock output, Bank A.
Ground.
Buffered clock output, Bank B.
Buffered clock output, Bank B.
www.DataSheet4U.com NB2304A 3.3 V Zero Delay Clock Buffer The NB2304A is a versatile, 3.3 V zero delay buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom and other high performance applications.
It is available in an 8 pin package.
The part has an on chip PLL which locks to an input clock presented on the REF pin.
The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs.
The input to
NB2304A Features
* http://onsemi.com MARKING DIAGRAM
* 8 8 1 SOIC
* 8 D SUFFIX CASE 751 1 XXXX ALYW G XXXX A L Y W G = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb
* Free Package
* For additional marking information, refer to Application Note AND8002/D.
* Zero Input
