Description
m o .c 4U 2.5V / 3.3V tMultilevel Input to e Differential e LVPECL/LVNECL h Clock or S Data a t Receiver/Driver/Translator a Buffer .D w The NB6L16 is.
Pin 1 2 Name NC D I/O.
LVDS, CML, LVPECL, LVNECL, LVTTL, LVCMOS Input LVDS, CML, LVPECL, LVNECL, LVTTL, LVCMOS Input.
ECL.
Features
* perature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Vth is applied to the complementary input when operating in single
* ended
Applications
* Input accept LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. Outputs are 800 mV ECL signals. The VBB pin, an internally generated voltage supply, is available to this device only. For single
* ended input conditions, the unused differential input is connected to VBB