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NB6N11S

Input to LVDS Fanout Buffer/Translator

NB6N11S Features

* Maximum Input Clock Frequency > 2.0 GHz

* Maximum Input Data Rate > 2.5 Gb/s

* 1 ps Maximum of RMS Clock Jitter

* Typically 10 ps of Data Dependent Jitter

* 380 ps Typical Propagation Delay

* 120 ps Typical Rise and Fall Times

* Functionally

NB6N11S General Description

The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical copies of Clock or Data will be distributed, operating up to 2.0 GHz or 2.5 Gb/s, respectively. As such, th.

NB6N11S Datasheet (314.24 KB)

Preview of NB6N11S PDF

Datasheet Details

Part number:

NB6N11S

Manufacturer:

ON Semiconductor ↗

File Size:

314.24 KB

Description:

Input to lvds fanout buffer/translator.

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TAGS

NB6N11S Input LVDS Fanout Buffer Translator ON Semiconductor

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