NB6N11S Datasheet (ON Semiconductor) - Input to LVDS Fanout Buffer/Translator

NB6N11S, Input to LVDS Fanout Buffer/Translator

The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS.

These signals will be translated to LVDS and two identical copies of Clock or Data will be distributed, operating up to 2.0 GHz or 2.5 Gb/s, respectively.

As such, th

NB6N11S Features

* Maximum Input Clock Frequency > 2.0 GHz

* Maximum Input Data Rate > 2.5 Gb/s

* 1 ps Maximum of RMS Clock Jitter

* Typically 10 ps of Data Dependent Jitter

* 380 ps Typical Propagation Delay

* 120 ps Typical Rise and Fall Times

* Functionally