NB6N14S Datasheet (ON Semiconductor) - Differential Input to LVDS Fanout Buffer/Translator

NB6N14S, Differential Input to LVDS Fanout Buffer/Translator

Pin Name I/O Description 1 Q1 LVDS Output Non *inverted IN output.

Typically loaded with 100 W receiver termination resistor across differential pair.

2 Q1 LVDS Output Inverted IN output.

Typically loaded with 100 W receiver termination resistor across differential pair.

3 Q2 L

NB6N14S 3.3 V 1:4 AnyLevelt Differential Input to LVDS Fanout Buffer/Translator The NB6N14S is a differential 1:4 Clock or Data Receiver and will accept AnyLevelt differential input signals: LVPECL, CML or LVDS.

These signals will be translated to LVDS and four identical copies of Clock or Data will be distributed, operating up to 2.0 GHz or 2.5 Gb/s, respectively.

As such, the NB6N14S is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution applications.

The NB6N1

NB6N14S Features

* Maximum Input Clock Frequency > 2.0 GHz

* Maximum Input Data Rate > 2.5 Gb/s

* 1 ps Maximum RMS Clock Jitter

* Typically 10 ps Data Dependent Jitter

* 380 ps Typical Propagation Delay

* 120 ps Typical Rise and Fall Times

* VREF_AC Reference O