NCP5210 Datasheet - ON Semiconductor

NCP5210 - PWM Dual Buck and Linear DDR Power Controller

Pin Symbol 1 COMP 2 FBDDQ 3 SS 4 PGND 5 VTT 6 VDDQ 7 AGND 8 FBVTT 9 DDQ_REF 10 FB1P5 11 GND_1P5 12 BG_1P5 13 TG_1P5 14 BUF_Cut 15 COMP_1P5 16 5VDUAL 17 BOOT 18 TG_DDQ 19 BG_DDQ 20 SW_DDQ 21 TH_PAD Description VDDQ error amplifier compensation node.

DDQ re

NCP5210 3 in 1 PWM Dual Buck and Linear DDR Power Controller The NCP5210, 3 in 1 PWM Dual Buck and Linear DDR Power Controller, is a complete power solution for MCH and DDR memory.

This IC combines the efficiency of PWM controllers for the VDDQ supply and the MCH core supply voltage with the simplicity of linear regulator for the VTT termination voltage.

This IC contains two synchronous PWM buck controller for driving four external N Ch FETs to form the D

NCP5210 Features

* include, soft

* start circuitry, undervoltage monitoring of 5VDUAL and BOOT voltage, and thermal shutdown. The device is housed in a thermal enhanced space

* saving QFN

* 20 package. Features

* Incorporates Synchronous PWM Buck Controllers for VDDQ and VMCH

* Integr

NCP5210_ONSemiconductor.pdf