8SLVD2102 Datasheet - Renesas

Dual 1:2 LVDS Output Fanout Buffer

8SLVD2102 Features

* Two 1:2, low skew, low additive jitter LVDS fanout buffers

* Two differential clock inputs

* Differential pairs can accept the following differential input levels: LVDS and LVPECL

* Maximum input clock frequency: 2GHz

* Output bank skew: 15ps (maximum)

8SLVD2102 General Description

The 8SLVD2102 is a high-performance differential dual 1:2 LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD2102 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-par.

8SLVD2102 Datasheet (752.65 KB)