8T73S208B-01 Differential LVPECL Clock Divider and Fanout Buffer

Renesas

Description

2.5 V, 3.3 V Differential LVPECL Clock Divider and Fanout Buffer 8T73S208B-01 Datasheet General .
The 8T73S208B-01 is a high-performance differential LVPECL clock divider and fanout buffer.

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Datasheet Specifications

Part number: 8T73S208B-01
Manufacturer: Renesas ↗
File Size: 559.66 KB
Datasheet: 8T73S208B-01-Renesas.pdf
Description: Differential LVPECL Clock Divider and Fanout Buffer

Features

* One differential input reference clock
* Differential pair can accept the following differential input levels: LVDS, LVPECL, CML
* Integrated input termination resistors
* Eight LVPECL outputs
* Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8

Applications

* demanding well-defined performance and repeatability. The integrated input termination resistors make interfacing to the reference source easy and reduce passive component count. Each output can be individually enabled or disabled in the high-impedance state controlled by a I2C register. On power-up

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8T73S208B-01 Differential LVPECL Clock Divider and Fanout Buffer Renesas

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