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8T74S208B - LVDS Clock Divider and Fanout Buffer

8T74S208B Description

2.5V Differential LVDS Clock Divider and Fanout Buffer 8T74S208B Datasheet .
The 8T74S208B is a high-performance differential LVDS clock divider and fanout buffer.

8T74S208B Features

* One differential input reference clock
* Differential pair can accept the following differential input levels: LVDS, LVPECL, CML
* Integrated input termination resistors
* Eight LVDS outputs
* Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8

8T74S208B Applications

* demanding well-defined performance and repeatability. The integrated input termination resistors make interfacing to the reference source easy and reduce passive component count. Each output can be individually enabled or disabled in the high-impedance state controlled by a I2C register. On power-up

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Datasheet Details

Part number
8T74S208B
Manufacturer
Renesas ↗
File Size
632.27 KB
Datasheet
8T74S208B-Renesas.pdf
Description
LVDS Clock Divider and Fanout Buffer

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