8T74S208B

LVDS Clock Divider and Fanout Buffer

Renesas

8T74S208B Features

* One differential input reference clock

* Differential pair can accept the following differential input levels: LVDS, LVPECL, CML

* Integrated input termination resistors

* Eight LVDS outputs

* Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8

8T74S208B General Description

The 8T74S208B is a high-performance differential LVDS clock divider and fanout buffer. The device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks. The 8T74S208B is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and pa.

8T74S208B Datasheet (632.27 KB)

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Datasheet Details

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8T74S208B

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Renesas ↗

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632.27 KB

Description:

Lvds clock divider and fanout buffer.

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8T74S208B LVDS Clock Divider and Fanout Buffer Renesas

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8T74S208B Features

8T74S208B General Description

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