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ICS98UAE877A Datasheet - Renesas

ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER

The PLL clock buffer, ICS98UAE877A, is designed for a VDDQ of 1.5V, an AVDD of 1.5V and differential data input and output levels. ICS98UAE877A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) .

ICS98UAE877A Features

* Low skew, low jitter PLL clock driver

* 1 to 10 differential clock distribution

* Feedback pins for input to output synchronization

* Spread Spectrum tolerant inputs

* Auto PD when input signal is at a certain logic state

* Available in 52-ball VFBGA

ICS98UAE877A-Renesas.pdf

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Datasheet Details

Part number:

ICS98UAE877A

Manufacturer:

Renesas ↗

File Size:

403.20 KB

Description:

1.5v low-power wide-range frequency clock driver.

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ICS98UAE877A ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER Renesas

ICS98UAE877A Distributor