IDT23S09 Datasheet (Renesas) - 3.3V ZERO DELAY CLOCK BUFFER

IDT23S09 Description

The IDT23S09 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applicationsThe zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.

The IDT23S09 is a 16-pin vers

Features

* Phase-Lock Loop Clock Distribution

* 10MHz to 133MHz operating frequency

* Distributes one clock input to one bank of five and one bank of four outputs

* Separate output enable for each output bank

* Output Skew < 250ps

* Low jitter

IDT23S09 Datasheet - Renesas

IDT23S09, 3.3V ZERO DELAY CLOCK BUFFER