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MK2049-45

CLOCK PLL

MK2049-45 Features

* Packaged in 20-pin SOIC

* 3.3 V + 5% operation

* Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E

* Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50

MK2049-45 General Description

The MK2049-45A is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication. Basic configur.

MK2049-45 Datasheet (229.39 KB)

Preview of MK2049-45 PDF

Datasheet Details

Part number:

MK2049-45

Manufacturer:

Renesas ↗

File Size:

229.39 KB

Description:

Clock pll.

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TAGS

MK2049-45 CLOCK PLL Renesas

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