K7P321874C Datasheet - Samsung Electronics

K7P321874C 1Mx36 & 2Mx18 SRAM

The K7P323674C and K7P321874C are 37,748,736 bit Synchronous Pipeline Mode SRAM. It is organized as 1,048,576 words of 36 bits(or 2,097,152 words of 18 bits)and is implemented in SAMSUNG′s advanced CMOS technology. Single differential HSTL level K clocks are used to initiate the read/write operation.

K7P323674C K7P321874C Preliminary www.DataSheet4U.com 1Mx36 & 2Mx18 SRAM 32Mb C-die LW SRAM Specification 119BGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON .

K7P321874C Features

* 1Mx36 or 2Mx18 Organizations.

* 1.8 or 2.5V VDD/1.5V ~1.8VDDQ.

* HSTL Input and Output Levels.

* Differential, HSTL Clock Inputs K, K.

* Synchronous Read and Write Operation

* Registered Input and Registered Output

* Internal Pipeline Latches

K7P321874C_SamsungElectronics.pdf