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K4X51323PC-8G - 16M x32 Mobile-DDR SDRAM

This page provides the datasheet information for the K4X51323PC-8G, a member of the K4X51323PC-7E 16M x32 Mobile-DDR SDRAM family.

Description

Clock : CK and CK are differential clock inputs.

All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK.

Internal clock signals are derived from CK/CK.

Features

  • Mobile-DDR SDRAM.
  • 1.8V power supply, 1.8V I/O power.
  • Double-data-rate architecture; two data transfers per clock cycle.
  • Bidirectional data strobe(DQS).
  • Four banks operation.
  • 1 /CS.
  • 1 CKE.
  • Differential clock inputs(CK and CK).
  • MRS cycle with address key programs - CAS Latency ( 2, 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave) - Partial Self Refresh Type ( Full, 1/2, 1/4 Array ) - Output Driver St.

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Datasheet Details

Part number K4X51323PC-8G
Manufacturer Samsung semiconductor
File Size 287.19 KB
Description 16M x32 Mobile-DDR SDRAM
Datasheet download datasheet K4X51323PC-8G Datasheet
Additional preview pages of the K4X51323PC-8G datasheet.

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Full PDF Text Transcription

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Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM www.DataSheet4U.com 16M x32 Mobile-DDR SDRAM 1 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Document Title 16M x32 Mobile-DDR SDRAM Mobile-DDR SDRAM Revision History Revision No. History 0.0 0.1 0.2 - First version for target specification - Insertion of PKG dimension of 90FBGA JEDEC Standard type. - Preliminary Datasheet - Insertion DC Current value. - Changing Frequency from DDR333/DDR266 to DDR266/DDR222. - Updating DC current value. - Changing expression of PKG dimension. - Changing format with JEDEC standard type. - Insertion of Normal power bin. - Changing IDD3P/3PS - Changing IDD6 limit. - Define maximum burst refresh cycle. - Add a note related with Vdd & Vddq. - Add a note related with IDD8.
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