The K6R1004C1C is a 1,048,576-bit high-speed Static Random Access Memory organized as 262,144 words by 4 bits.
The K6R1004C1C uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.
The device is fabricated using SAMSUNG′s advan
www.DataSheet4U.com PRELIMINARY PRELIMINARY CMOS SRAM K6R1004C1C-C/C-L, K6R1004C1C-I/C-P Document Title 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating).
Revision History Rev.
No.
Rev.
0.0 Rev.
1.0 History Initial release with Preliminary.
Release to Final Data Sheet.
1.1.
Delete Preliminary.
Add 10ns & Low Power Ver.
Delete 20ns speed bin Draft Data Aug.
5.
1998 Mar.
3.
1999 Remark Preliminary Final Rev.
2.0 Rev.
3.0 Apr.
24.
2000 Sep.
24.
2001 Final Final The attached dat
K6R1004C1C Features
* Fast Access Time 10,12,15ns(Max.)
* Low Power Dissipation Standby (TTL) : 30mA(Max.) (CMOS) : 5mA(Max.) 0.5mA(Max.) L-Ver. only Operating K6R1004C1C-10 : 75mA(Max.) K6R1004C1C-12 : 70mA(Max.) K6R1004C1C-15 : 68mA(Max.)
* Single 5.0V±10% Power Supply
* TTL Compatible
K6R1004C1C_Samsungsemiconductor.pdf
Datasheet Details
K6R1004C1C
Samsung semiconductor
126.75 KB
High-speed cmos static ram.
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